In the semiconductor art, it is desirable to improve transistor performance even as devices become smaller due to ongoing reductions in device scale. Further, it is desirable to manufacture integrated circuit semiconductor devices that incorporate transistors for low, high and sometimes medium voltage range applications in a single integrated circuit. For example, in the cellphone field it is desirable to use semiconductor devices designed and manufactured for providing logic functions and also including display driver circuitry, such as LCD driver circuitry, in a single integrated circuit (“IC”). While the transistors on such an integrated circuit, often referred to as a “system on a chip” (abbreviated “SOIC” or “SOC” or “SoC”) include transistors for logic functions which operate at very low voltages, as low as 1.8 Volts or 2.5 Volts, other transistors fabricated on the same integrated circuit device are designed for high power applications and operate at high voltages, as high as 30 or even 40 Volts from drain to source. These high voltage transistor devices also are capable of carrying far more current than the logic transistors or periphery transistors typically used in digital circuits.
One form of high voltage transistor important in system applications such as cellphones and wireless circuitry is the lateral double-diffused MOS or LDMOS transistor. For example, U.S. Pat. No. 6,265,752 issued Jul. 24, 2001, and assigned to the assignee of the present invention, herein incorporated by reference (the “752 patent”) describes lateral DMOS devices formed in epitaxial well regions over an N+ buried layer. The high voltage transistor (or transistors) of the '752 patent has a source formed in a first well region, a gate overlying both the first well region and a second well region of an opposite dopant type, and an oxide formed within the area bounded by the second well and isolating the remainder of the gate from the source formed in the second well. This type of high voltage or power transistor can handle operating voltages of 30, 40 or more volts and is therefore particularly useful for driving displays, as for cellphones with liquid crystal displays (LCDs), for automotive applications, and the like.
In the prior art, a problem which arises particularly with such SOC integrated circuits including both low and high voltage MOS devices in a single piece of silicon substrate is that the high voltage LDMOS transistors fabricated in such devices often exhibit a “hump” or undesirable discontinuity in the Id (drain current) vs. Vg (gate voltage) current-voltage characteristic. This Id-Vg “hump” is an undesirable electrical characteristic and results in less than desirable performance, or even unacceptable performance, in the completed devices. That is, the actual operation of the devices deviates from the expected, and designed for, operation.
In current CMOS SOC technology, shallow trench isolation (STI) is becoming the typical approach to creating oxide isolation regions, which allow various types of transistors to be integrated onto a single device by creating electrically isolated active areas within the silicon substrate. In fabricating highly integrated devices incorporating a variety of types of transistors, these different areas of an integrated circuit may be subjected to asymmetric semiconductor processing steps by masking one region with an oxide, hard mask or photoresist coating, while subjecting another region to different process steps, so that devices with different doping profiles, different dielectric materials, and different etching processes can be produced on a single semiconductor substrate, which becomes one or more integrated circuits. The oxide pattern density, that is the ratio of the amount of active area vs. oxide isolation in a given region of the substrate may also vary for the various device types. Although shallow trench isolation (STI) is rapidly becoming the prevalent isolation method, other isolation methods such as local oxidation of silicon (LOCOS), rapid thermal oxidation or TEOS may also be used to form isolation oxide regions between active areas.
A paper entitled “Analysis of Width Edge Effects in Advanced Isolation Schemes for Deep Submicron CMOS Technologies”, by P. Sallagoity, et al., IEEE Transactions on Electron Devices, Vol. 43, No. 11, November 1996, pp. 1900–1906, describes several possible causes for the “hump” in the Id-Vg characteristic. In the paper, simulations of the effects of the abrupt transition angle at the active area/isolation boundaries are studied. The paper concludes that if the transition from a device active area to the oxide isolation region is too abrupt, then for certain devices, a subthreshold current flow in the adjacent transistor increases due to a corner parasitic effect at the transition boundary from the active area to the isolation. That is, as the transistor gate voltage is increased but, before it reaches the designed threshold voltage Vt where source-drain current is to be conducted, subthreshold drain current begins to flow due to a parasitic transistor at the corner of the isolation region. As a result of the parasitic or “corner effect” transistor formed at the transition region in the channel, the device turns on early (before the gate voltage Vg is greater than the device threshold voltage) and the resulting undesired current flow creates the “hump” in the drain current vs. gate voltage characteristic (Id v. Vg curve). An illustrative plot of the Id-Vg curves for a device exhibiting the “hump” and for a device, which does not exhibit the “hump” in the current-voltage characteristic, is shown in FIGS. 1a and 1b, respectively.
While the abrupt isolation transition may be observed when using any isolation type including field oxide, LOCOS or shallow trench isolation (STI) as the isolation scheme for the oxide, STI trenches form the most abrupt active-area-to-isolation region transition angles and therefore the observed corner effects may be expected to be greater in devices fabricated with this current isolation technology. As mentioned above, STI is rapidly becoming the state-of-the-art isolation scheme.
A need thus exists for a method and apparatus for fabricating a high voltage transistor that has an Id-Vg electrical characteristic without the undesirable subthreshold current problem, or “hump”, of the prior art. The high voltage transistors should be manufacturable using semiconductor processes that are compatible with typical semiconductor processes for other device types, so that integrated SoC or SoIC devices may be fabricated including both low voltage and high voltage transistors. The various methods and the apparatus of the present invention address these needs.